1. Field of the Invention
The present invention relates to a method for reducing power consumption of a plasma display panel (PDP), and more particularly, to a method for improving efficiency of power recovery of a PDP.
2. Description of the Prior Art
Plasma display panels are thin panels that can display over a large screen. Therefore, they are rapidly gaining popularity in the new large-panel market. The working principle of a plasma display panel (PDP) is to excite electric charges in the plasma by charging the PDP with a high frequency alternating voltage. In the activating process, ultraviolet rays are emitted to excite the phosphor on the tube wall for emitting light. The plasma display panel behaves like a capacitor. When two electrodes of the PDP are suddenly short-circuited or charged by the high voltage, an inrush current will be generated which will induce a great loss of energy. This is a problem which the driving circuit of the plasma display panel must rectify. In order to reduce the inrush current, the sustain driver of a traditional plasma display panel uses an energy recovery circuit (ERC) that has an inductor resonating with the intrinsic capacitor of the PDP to reduce power consumption.
Please refer to FIG. 1, which is a circuit diagram of an energy recovery circuit of a sustain driver of a plasma display panel (PDP) 10 according to the prior art. The energy recovery circuit has a first driver 20 and a second driver 30 respectively connected to two sides of the PDP 10 to provide the sustain voltage Vs to the PDP 10. The PDP 10 is represented as a panel capacitor Cp in FIG. 1. The first driver 20 has a first driving unit 22 and a first recovery unit 24. The first driving unit 22 has two switches SW1 and SW2. The first recovery unit 24 has two diodes (D1, D2), two switches (SW5, SW6), a first inductor Lx, and a first recovery capacitor Cx. One end of the switch SW1 is connected to a first bias terminal Vs, and the other end of the switch SW1 is connected to the first inductor Lx, the switch SW2, and the left electrode of the panel capacitor Cp. The switch SW2 and the first recovery capacitor Cx are connected to the ground terminal GND, i.e. the second bias terminal. The other end of the first recovery capacitor Cx is connected the switches SW5 and SW6. The switch SW5 is connected to the diode D1 in series and then to the first recovery capacitor Cx, the first inductor Lx, and the diode D2. The diode D2 is connected to the switch SW6 in series and then to the first recovery capacitor Cx, the first inductor Lx, and the diode D1. The second driver 30 has a circuit structure that is symmetric with the first driver 20. The second driver 30 has a second driving unit 32 and a second recovery unit 34. The second driving unit 32 has two switches SW3 and SW4. The second recovery 34 has two diodes (D3, D4), two switches (SW7, SW8), a second inductor Ly, and a second recovery capacitor Cy.
Please refer to FIGS. 1-2. FIG. 2 is a timing diagram of control signals used to control the first control circuit 20 and the second control circuit 30 within a working period of the PDP according to the prior art. Within the period t3-t4, the stored energy of the panel capacitor Cp is transferred to the second recovery unit 34, and the second driving unit 32 drives the voltage Vy on the right electrode of the panel capacitor Cp from Vs to the ground level. The switches SW1 and SW8 are turned on to form a series resonance loop l1 that passes through the panel capacitor Cp, the second inductor Ly, the diode D4, and the second recovery capacitor Cy so that the second recovery capacitor Cy is charged by the panel capacitor Cp. In an ideal condition, before turning on the SW4, due to the resonance loop l1, the voltage level of the second recovery capacitor Cy should be pulled up to Vs/2 and the voltage Vy should be pulled down to the ground level. However, because of high-frequency capacitance effect, inductance effect, and resistance effect, the voltage level of the second recovery capacitor Cy is pulled up to (Vs/2−ΔV1) and the voltage Vy is actually pulled down to ΔV2, where both ΔV1 and ΔV2 are positive voltages and ΔV1 is less than Vs/2. Therefore, when the switch SW4 is turned on to make the right electrode of the panel capacitor Cp connect to the ground terminal GND, the voltage Vy is pulled down from ΔV2 to the ground level. The electric energy, hence, is wasted while the right electrode of the panel 10 is connected to the ground terminal GND.
Please refer to FIGS. 2-3. FIG. 3 indicates the status of the drivers 20 and 30 within the period t5-t7. Within the period t5-t7, energy stored in the second recovery capacitor Cy within the period t3-t4 is recovered to the panel capacitor Cp so that voltage Vy of the right electrode of the panel 10 is pulled up from the ground level. The switches SW1 and SW2 are turned on to form a series resonance loop l2 that passes through the second recovery capacitor Ly, the diode D3, the second inductor Ly, and the panel capacitor Cp so that the panel capacitor Cp is charged by the second recovery circuit Cy. In the ideal condition, the voltage Vy should be pulled up to the sustain voltage Vs. However, because of the high-frequency capacitance effect, the inductance effect, and the resistance effect, the voltage Vy is actually pulled up to approximately (Vs−2ΔV1). Therefore, after the time t7 when the switch SW3 is turned on, the voltage Vy is pulled up from (Vs−2ΔV1) to Vs. The electric energy, hence, is wasted while the right electrode of the panel 10 is connected to the first bias terminal Vs.
Please refer to FIGS. 2 and 4. FIG. 4 indicates the status of the drivers 20 and 30 within the period t7-t8. Within the period t7-t8, the stored energy of the panel capacitor Cp is transferred to the first recovery unit 24, and the first driving unit 22 drives the voltage Vy on the left electrode of the panel capacitor Cp from Vs. The switches SW3 and SW6 are turned on to form a series resonance loop l3 that passes through the panel capacitor Cp, the first inductor Lx, the diode D2, and the first recovery capacitor Cx so that the second first capacitor Cx is charged by the panel capacitor Cp. In the ideal condition, before turning on the SW2, the voltage level of the first recovery capacitor Cx should be pulled up to Vs/2 and the voltage Vx should be pulled down to the ground level. However, due to the high-frequency capacitance effect, the inductance effect, and the resistance effect, the voltage level of the first recovery capacitor Cx is pulled up to (Vs/2−ΔV1) and the voltage Vy is actually pulled down to ΔV2. Therefore, when the switch SW2 is turned on to make the left electrode of the panel capacitor Cp connect to the ground terminal GND, the voltage Vx is pulled down from ΔV2 to the ground level. The electric energy, hence, is wasted while the left electrode of the panel 10 is connected to the ground terminal GND.
Please refer to FIGS. 2 and 5. FIG. 5 indicates the status of the drivers 20 and 30 within the period t1-t3. Within the period t1-t3, energy stored in the first recovery capacitor Cx within the period t7-t8 of previous working period is recovered to the panel capacitor Cp so that voltage Vx of the left electrode of the panel 10 is pulled up from the ground level. The switches SW3 and SW5 are turned on to form a series resonance loop l4 that passes through the first recovery capacitor Lx, the diode D1, the first inductor Lx, and the panel capacitor Cp so that the panel capacitor Cp is charged by the first recovery circuit Cx. In the ideal condition, the voltage Vx should be pulled up to Vs. However, because of the high-frequency capacitance effect, the inductance effect, and the resistance effect, the voltage Vx is actually pulled up to approximately (Vs−2ΔV1). Therefore, after the time t3 when the switch SW1 is turned on, the voltage Vx is pulled up from (Vs−2ΔV1) to Vs. The electric energy, hence, is wasted while the left electrode of the panel 10 is connected to the first bias terminal Vs.
Briefly summarized, due to high-frequency capacitance effect, inductance effect, and resistance effect, the prior art method fails to achieve zero-voltage switching (ZVS) when adjusting the voltage Vx and Vy to Vs or to the ground level before the corresponding electrode connecting to the first bias terminal Vs or to the ground terminal GND.